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PRELIMINARY
K6R1004C1A-C
Document Title
256Kx4 High Speed Static RAM(5V Operating), Revolutionary Pin out.
CMOS SRAM
Revision History
Rev. No. Rev. 0.0 Rev. 1.0 History Initial release with Preliminary. Release to final Data Sheet. 1.1. Delete Preliminary Update D.C parameters. 2.1. Update D.C parameters. Previous spec. Items (12/15/17/20ns part) Icc 200/190/180/170mA Isb 30mA Isb1 10mA Draft Data Apr. 22th, 1995 Feb. 29th, 1996 Remark Preliminary Final
Rev. 2.0
Jul. 16th, 1996 Updated spec. (12/15/17/20ns part) 150/145/145/140mA 25mA 8mA Jun. 2nd, 1997
Final
Rev. 3.0
Add Industrial Temperature Range parts. 3.1. Add Industrial Temperature Range parts with the same parameters as Commercial Temperature Range parts. 3.1.1. Add K6R1004C1A parts for Industrial Temperature Range. 3.1.2. Add ordering information. 3.1.3. Add the condition for operating at Industrial Temp. Range. 3.2. Add the test condition for VOH1 with VCC=5V5% at 25C 3.3. Add timing diagram to define tWP as (Timing Wave Form of Write Cycle(CS=Controlled) 4.1. Delete Industrial Temperature Range Part 4.2. Delete TSOP2 Package 4.3. Delete 17ns Part
Final
Rev. 4.0
Feb. 25th, 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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Rev 4.0 February 1998
PRELIMINARY
K6R1004C1A-C
256K x 4 Bit (with OE)High-Speed CMOS Static RAM
FEATURES
* Fast Access Time 12, 15, 20ns(Max.) * Low Power Dissipation Standby (TTL) : 25mA(Max.) (CMOS) : 8mA(Max.) Operating K6R1004C1A-12 : 150mA(Max.) K6R1004C1A-15 : 145mA(Max.) K6R1004C1A-20 : 140mA(Max.) * Single 5.0V10% Power Supply * TTL Compatible Inputs and Outputs * I/O Compatible with 3.3V Device * Fully Static Operation - No Clock or Refresh required * Three State Outputs * Center Power/Ground Pin Configuration * Standard Pin Configuration K6R1004C1A-J : 32-SOJ-400
CMOS SRAM
GENERAL DESCRIPTION
The K6R1004C1A is a 1,048,576-bit high-speed Static Random Access Memory organized as 262,144 words by 4 bits. The K6R1004C1A uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNGs advanced CMOS process and designed for highspeed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R1004C1A is packaged in a 400 mil 32-pin plastic SOJ.
PIN CONFIGURATION(Top View)
N.C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 A17 31 A16 30 A15 29 A14 28 A13 27 OE
FUNCTIONAL BLOCK DIAGRAM
A0 A1 A2 A3
Clk Gen.
A0 A1 A3 A4 A5 A6 A7 A8 A2
Pre-Charge Circuit
CS I/O1 Vcc
26 I/O4
SOJ
25 Vss 24 Vcc 23 I/O3 22 A12 21 A11 20 A10 19 18 A9 A8
Row Select
Vss
Memory Array 512 Rows 512x4 Columns
I/O2 WE A4 A5 A6 A7
I/O1~I/O4
Data Cont. CLK Gen.
A9
I/O Circuit & Column Select
N.C
17 N.C
A10 A12 A14 A16 A11 A13 A15 A17
PIN FUNCTION
Pin Name Pin Function Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+5.0V) Ground No Connection A0 - A17 WE CS OE I/O1~I/O4 VCC VSS N.C
CS WE OE
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Rev 4.0 February 1998
PRELIMINARY
K6R1004C1A-C
ABSOLUTE MAXIMUM RATINGS*
Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Symbol VIN, VOUT VCC PD TSTG TA Rating -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70 Unit V V W C C
CMOS SRAM
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70C)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.5* Typ 5.0 0 Max 5.5 0 VCC+0.5** 0.8 Unit V V V V
* VIL(Min) = -2.0V a.c(Pulse Width 10ns) for I 20mA. ** VIH(Max) = VCC + 2.0V a.c (Pulse Width 10ns) for I 20mA.
DC AND OPERATING CHARACTERISTICS(TA=0 to 70C, Vcc=5.0V10%, unless otherwise specified)
Parameter Input Leakage Current Output Leakage Current Operating Current Symbol ILI ILO ICC Test Conditions VIN = VSS to VCC CS=VIH or OE=VIH or WE=VIL VOUT = VSS to VCC Min. Cycle, 100% Duty CS=VIL, VIN=VIH or VIL, IOUT=0mA Min. Cycle, CS=VIH f=0MHz, CSVCC-0.2V, VINVCC-0.2V or VIN0.2V IOL=8mA IOH=-4mA IOH1=-0.1mA 12ns 15ns 20ns Standby Current ISB ISB1 Output Low Voltage Level Output High Voltage Level VOL VOH VOH1*
* VCC=5.0V5%, Temp =25C
Min -2 -2 2.4 -
Max 2 2 150 145 140 25 8 0.4 3.95
Unit A A mA
mA mA V V V
CAPACITANCE*(TA=25C, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol CI/O CIN
Test Conditions VI/O=0V VIN=0V
MIN -
Max 8 6
Unit pF pF
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Rev 4.0 February 1998
PRELIMINARY
K6R1004C1A-C
AC CHARACTERISTICS(TA=0 to 70C, VCC=5.0V10%, unless otherwise noted.)
TEST CONDITIONS
Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads Value 0V to 3V 3ns 1.5V See below
CMOS SRAM
Output Loads(A) +5.0V 480 DOUT 255 30pF*
Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5.0V 480 DOUT 255 5pF*
* Including Scope and Jig Capacitance
READ CYCLE
Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Chip Selection to Power Up Time Chip Selection to Power DownTime Symbol tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tPU tPD K6R1004C1A-12 Min 12 3 0 0 0 3 0 Max 12 12 6 6 6 12 K6R1004C1A-15 Min 15 3 0 0 0 3 0 Max 15 15 7 7 7 15 K6R1004C1A-20 Min 20 3 0 0 0 3 0 Max 20 20 9 9 9 20 Unit ns ns ns ns ns ns ns ns ns ns ns
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Rev 4.0 February 1998
PRELIMINARY
K6R1004C1A-C
WRITE CYCLE
Parameter Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width(OE High) Write Pulse Width(OE Low) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Symbol tWC tCW tAS tAW tWP tWP1 tWR tWHZ tDW tDH tOW K6R1004C1A-12 Min 12 8 0 8 8 12 0 0 6 0 3 Max 6 K6R1004C1A-15 Min 15 10 0 10 10 15 0 0 7 0 3 Max 7 K6R1004C1A-20 Min 20 12 0 12 12 20 0 0 9 0 3 Max 9 Unit ns ns ns ns ns ns ns ns ns ns ns
CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
Address tOH Data Out Previous Valid Data tAA Valid Data
(Address Controlled, CS=OE=VIL, WE=VIH)
tRC
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC Address tAA tCO tOE OE tOLZ tLZ(4,5) Valid Data ICC ISB tPU 50% tPD 50% tOH tHZ(3,4,5)
CS
tOHZ
Data out VCC Current
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Rev 4.0 February 1998
PRELIMINARY
K6R1004C1A-C
NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
tWC Address tAW OE tCW(3) CS tAS(4) WE tDW Data in High-Z tOHZ(6) Data out High-Z(8) Valid Data tDH tWP(2) tWR(5)
TIMING WAVEFORM OF WRITE CYCLE(2)
(OE=Low Fixed)
tWC Address tAW tCW(3) CS tAS(4) WE tDW Data in High-Z tWHZ(6) Data out High-Z(8) Valid Data tOW
(10) (9)
tWR(5)
tWP1(2)
tDH
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Rev 4.0 February 1998
PRELIMINARY
K6R1004C1A-C
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
tWC Address tAW tCW(3) CS tAS(4) WE tDW Data in tDH tWP(2) tWR(5)
CMOS SRAM
High-Z
tLZ tWHZ(6)
Valid Data
High-Z
Data out
High-Z
High-Z(8)
NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
CS H L L L
* X means Dont Care.
WE X H H L
OE X* H L X
Mode Not Select Output Disable Read Write
I/O Pin High-Z High-Z DOUT DIN
Supply Current ISB, ISB1 ICC ICC ICC
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Rev 4.0 February 1998
PRELIMINARY
K6R1004C1A-C
PACKAGE DIMENSIONS
32-SOJ-400
#32 #17
CMOS SRAM
Units:millimeters/Inches
10.16 0.400
11.18 0.12 0.440 0.005
9.40 0.25 0.370 0.010
0.20 #1 21.36 MAX 0.841 20.95 0.12 0.825 0.005 ( 1.30 ) 0.051 ( 1.30 ) 0.051 0.43
+0.10 -0.05
+0.10 -0.05
#16 0.69 0.027 MIN
0.008 +0.004 -0.002
3.76 MAX 0.148
0.10 MAX 0.004
( 0.95 ) 0.0375
0.017 +0.004 -0.002
1.27 0.050
0.71
+0.10 -0.05
0.028 +0.004 -0.002
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Rev 4.0 February 1998

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